1. Isermann, R., Schaffnit, J., & Sinsel, S. (1999). Hardware-in-the-loop simulation for the design and testing of engine-control systems. Control Engineering Practice, 7(5), 643–653. In Figure 1, "Structure of a hardware-in-the-loop simulation," the diagram explicitly shows the "Real-time processor" (a real-time capable computer) as the central element connected to the physical ECU. The paper also discusses the application of HiL for testing under fault conditions (p. 644), which corresponds to electric error simulation.
2. Jung, K., Kim, T., & Park, K. (2013). A survey on hardware-in-the-loop simulation. 2013 13th International Conference on Control, Automation and Systems (ICCAS), 1730-1734. The paper's architectural overview in Section II, "HILS System," describes the main components, including the "real-time simulator" (real-time capable computer) and the "real target system" (the ECU, which requires a power supply). It also highlights the capability to simulate "abnormal conditions," which includes electric error simulation.
3. Gietelink, J., Ploeg, J., De Schutter, B., & Verhaegen, M. (2006). Development of a hardware-in-the-loop simulator for a cooperative adaptive cruise control system. 2006 IEEE Intelligent Transportation Systems Conference, 478-483. https://doi.org/10.1109/ITSC.2006.1706791. The paper describes the HiL setup (Section III-A), which is "built around a real-time computer" and includes the actual ECU hardware, which implicitly requires a power supply. The testing of failure modes is a primary use case.